https://dblp.org/pid/125/7792.html dblp person page RSS feed Mon, 15 Jul 2024 00:14:58 +0200 en-US daily 1 released under the CC0 1.0 license dblp@dagstuhl.de (dblp team) dblp@dagstuhl.de (dblp team) Computers/Computer_Science/Publications/Bibliographies http://www.rssboard.org/rss-specification https://dblp.org/img/logo.144x51.pnghttps://dblp.org/pid/125/7792.html14451 https://doi.org/10.1016/j.jpdc.2018.10.010Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé, Darío Suárez Gracia, Teresa Monreal Arnal, Pablo Ibáñez-Marín, Víctor Viñals Yúfera:
A fault-tolerant last level cache for CMPs operating at ultra-low voltage. J. Parallel Distributed Comput. 125: 31-44 (2019)]]>https://dblp.org/rec/journals/jpdc/Ferreron-Labari19Tue, 01 Jan 2019 00:00:00 +0100 http://arxiv.org/abs/1803.06955Alexandra Ferreron, Jesús Alastruey-Benedé, Darío Suárez Gracia, Ulya R. Karpuzcu:
AISC: Approximate Instruction Set Computer. CoRR abs/1803.06955 (2018)]]>https://dblp.org/rec/journals/corr/abs-1803-06955Mon, 01 Jan 2018 00:00:00 +0100 http://arxiv.org/abs/1803.09584Alexandra Ferreron, Radhika Jagtap, Sascha Bischoff, Roxana Rusitoru:
Crossing the Architectural Barrier: Evaluating Representative Regions of Parallel HPC Applications. CoRR abs/1803.09584 (2018)]]>https://dblp.org/rec/journals/corr/abs-1803-09584Mon, 01 Jan 2018 00:00:00 +0100 https://doi.org/10.1109/ISPASS.2017.7975275Alexandra Ferreron, Radhika Jagtap, Sascha Bischoff, Roxana Rusitoru:
Crossing the architectural barrier: Evaluating representative regions of parallel HPC applications. ISPASS 2017: 109-120]]>https://dblp.org/rec/conf/ispass/FerreronJBR17Sun, 01 Jan 2017 00:00:00 +0100 https://doi.org/10.1109/TC.2015.2479585Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Pablo Ibáñez:
Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage. IEEE Trans. Computers 65(3): 755-769 (2016)]]>https://dblp.org/rec/journals/tc/Ferreron-Labari16Fri, 01 Jan 2016 00:00:00 +0100 https://doi.org/10.1109/IISWC.2016.7581284Alexandra Ferreron, Radhika Jagtap, Roxana Rusitoru:
Identifying representative regions of parallel HPC applications: a cross-architectural evaluation. IISWC 2016: 223-224]]>https://dblp.org/rec/conf/iiswc/FerreronJR16Fri, 01 Jan 2016 00:00:00 +0100 https://doi.org/10.1145/2632217Darío Suárez Gracia, Alexandra Ferrerón-Labari, Luis Montesano Del Campo, Teresa Monreal Arnal, Víctor Viñals Yúfera:
Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping. ACM Trans. Archit. Code Optim. 11(2): 19:1-19:26 (2014)]]>https://dblp.org/rec/journals/taco/GraciaFCAY14Wed, 01 Jan 2014 00:00:00 +0100 https://doi.org/10.1109/SBAC-PAD.2014.12Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Víctor Viñals:
Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages. SBAC-PAD 2014: 238-245]]>https://dblp.org/rec/conf/sbac-pad/Ferreron-LabariGAAV14Wed, 01 Jan 2014 00:00:00 +0100 https://doi.org/10.1007/978-3-642-36424-2_22Alexandra Ferrerón-Labari, Marta Ortín-Obón, Darío Suárez Gracia, Jesús Alastruey-Benedé, Víctor Viñals Yúfera:
Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors. ARCS 2013: 256-267]]>https://dblp.org/rec/conf/arcs/Ferreron-LabariOSAY13Tue, 01 Jan 2013 00:00:00 +0100 https://doi.org/10.1145/2482759.2482765Marta Ortín, Alexandra Ferreron, Jorge Albericio, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals:
Characterization and cost-efficient selection of NoC topologies for general purpose CMPs. INA-OCMC@HiPEAC 2013: 21-24]]>https://dblp.org/rec/conf/hipeac/OrtinFAGVIV13Tue, 01 Jan 2013 00:00:00 +0100

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