Abstract
The drive to deliver increasingly powerful and feature-rich integrated circuits has made technology node scaling—the process of reducing transistor dimensions and increasing their density in microchips—a key challenge in the microelectronics industry. Historically, advances in optical lithography patterning have played a central role in allowing this trend to continue. Directed self-assembly of block copolymers is a promising alternative patterning technique that offers sub-lithographic resolution and reduced process complexity. However, the feasibility of applying this approach to the fabrication of critical device layers in future technology nodes has never been verified. Here we compare the use of directed self-assembly and conventional patterning methods in the fabrication of 7 nanometre node FinFETs, using an industrially relevant and high-volume manufacturing-compliant test vehicle. Electrical validation shows comparable device performance, suggesting that directed self-assembly could offer a simplified patterning technique for future semiconductor technology.
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Data availability
The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request.
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Acknowledgements
The authors would like to thank M. Colburn, M. Guillorn, S. Sieg, D. Sanders, J. Arnold, S. Burns, R. Allen, J. Pitera, R. Divakaruni, M. Khare and T. C. Chen for their technical and/or management support. The authors are grateful for all the support from their colleagues at IBM Albany NanoTech, including Alliance partners, IBM Almaden Research Center and IBM T. J. Watson Research Center. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities. Experimental materials used in this work were purchased from or provided by AZ (now EMD, a subsidiary of Merck) and JSR Micro, and greatly appreciated by the authors.
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C.-C.L. conceived and designed the experiments. E.F., Y.M., R.X., C.C., R.F. and C.-C.L. performed the material characterization, device fabrication and electron microscope image analysis. K.L. performed the device layout and optical proximity correction (OPC)-related analysis. C.W.Y., J.Z., C.Z and C.-C.L. performed the device measurements and data analysis. C.-C.L., H.T. and R.F. wrote the manuscript. All authors discussed the results and commented on the manuscript.
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Supplementary Notes 1–3, Supplementary Figures 1–3, and Supplementary Tables 1–3
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Liu, CC., Franke, E., Mignot, Y. et al. Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyond. Nat Electron 1, 562–569 (2018). https://doi.org/10.1038/s41928-018-0147-4
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DOI: https://doi.org/10.1038/s41928-018-0147-4
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